Posts Tagged ‘intel’

Show 22 –AppUp Show at SXSW Part 2: Featuring Intel Futurist, Brian David Johnson

The Intel AppUp show for developers “Show 22″: this episode is Part 2 of Bob and Rhonda’s adventure at SXSW Interactive Screenburn. In the first half of this episode, Bob and Rhonda chats with Intel Futurist, Brian David Johnson, about the awesome work that he does. As Intel’s first Futurist, Brian is responsible for understanding how people will interact with technology ten to fifteen years from now. In the second half of the show (04:18), Rhonda talks with Duane Allen from Spirepix Studios, and he shares his interests in using Ultrabook™ devices for his business.

Jeff’s Notebook: Released for vPro™ technology: Intel® Setup and Configuration Software 8.0

Good news for IT Managers and manageability software developers for Intel® vPro™ technology.  Our Intel vPro experts are constantly working our developer tools to improve the IT management of vPro client networks.  This week, they have released Intel Setup and Configuration Software (Intel® SCS) 8.0 to help IT managers and manageability software developers to set up and configure Intel® Active Management Technology features on systems with Intel Core™ vPro™ Processors.  Learn more about Intel SCS 8.0 and download it today.

Alles Neu macht der April!

Auch wenn wir hier in München einen zwischenzeitlichen Wintereinbruch gegeben hat, nähert sich doch nun endlich der Frühling und damit auch ein Start in viele Neuerungen – und wir warten nicht bis Mai, sondern fangen schon im April an! Also, was haben wir alles Neues zu berichten: Intel AppUp™ In-App Purchase: Content SDK Powered by Urban Airship*: Coole Geschichte, die InApp Purchasing Möglichkeiten wurden erweitert und nun können Inhalte wie Bücher, Videos, Musik usw. direkt aus der App heraus erworben werden, einfach in einer CSV Datei Informationen wie Preis, Währung, Beschreibung und ID eingeben. Das zusätzliche SDK inklusive der http://urbanairship.com/ Urban Airship Libraries ermöglichen das Einrichten von Inventories und natürlich den Download, der innerhalb der Anwendung veräußert werden soll. Die CSV Datei kann nach dem Upload der Inhalte auf das Urban Airship Portal generiert werden und diese sollte dann während dem Einreichungsprozess hochgeladen werden. Und das Beste daran ist, dass Intel die Kosten für die InApp purchases bis Ende März 2015 (!!) für registrierte Entwickler übernimmt, notwendig ist auch noch ein Urban Airship Account und schon kann es los gehen. Natürlich können Entwickler auch andere Hostingprovider nutzen, mit der Urban Airship Kooperation ist das ganze stärker an AppUp angepasst. Momentan ist das ganze nutzbar für html5 Apps, die durch den Encapsulator gejagt wurden und Anwendungen, welche das C++ SDK nutzen. Eine genaue Anleitung gibt es hier: Implementierung C++: appdeveloper.intel.com/en-us/article/implementing-app-purchase-content [EN] Implementierung WebApps: http://appdeveloper.intel.com/en-us/article/app-content-purchases-web-applications [EN] read more

First Commercial Intel Smartphone Lava XOLO X900 Launched Today

Today, the first Intel Smart phone XOLO X900 smartphone was launched in India  http://www.xolo.in/ Information Week Report http://www.wired.com/gadgetlab/2012/04/its-official-intel-silicon-to-finally-appear-in-a-shipping-smartphone-in-india/ According the official XOLO website: “Superior Intel technology and Lava’s innovation come together to bring you the new XOLO X900, the first smartphone with Intel Inside®. Experience fast web browsing with the 1.6 GHz Intel processor. Based on Intel patented Hyper Threading technology this processor also enables smooth multi-tasking with optimum battery usage. A 4.03” hi-resolution LCD screen, dedicated HDMI output, full HD 1080p playback and dual speakers ensure an unmatched multimedia experience. Click up to 10 photos in less than a second on the 8MP HD camera which boasts of certain DSLR like features. With XOLO X900’s 400 MHz Graphics Processing Unit, 3D and HD gaming turn immersively realistic. Everything you have always wanted, and more, now comes in a blink into your pocket” LAVA, one of India’s fastest growing handset brands.  XOLO X900, XOLO’s introductory offering, is the world’s first mobile phone with the power of Intel inside®.The stylish and sleek new XOLO X900 is a result of commitment to quality and innovation, designed to provide a superlative, immersing and engaging experience to address the need for a dynamic smartphone for today’s generation. The brand has invested in a state-of-the-art R&D Centre in Shenzhen (China) and Bangalore (India) Does Intel Chip use more power? To answer this, one of my colleague quickly looked at the battery life spec, and  you can find them from below. Datas from LAVA and Apple webpage: XOLO Talk time (2G) up to 15.5 hours Talk time (3G) up to 7.8 hours Music playback (earphones) up to 43.9 hours Video playback (earphones) up to 6 hours Total standby time up to 14 days iPhone 4 Spec: • Talk time: Up to 8 hours on 3G, up to 14 hours on 2G (GSM) • Standby time: Up to 200 hours • Internet use: Up to 6 hours on 3G, up to 9 hours on Wi-Fi • Video playback: Up to 10 hours • Audio playback: Up to 40 hours This  is pretty good considering a phone with 4.03” hi-resolution LCD screen, dedicated HDMI output, full HD 1080p playback!

Wellington and Austin: programming lots of cores

A couple of back-to-back opportunities to see great talks about harness lots of cores, and to give talks about programming options and why we do not need to give up on programmability in our quest for high performance. Wellington this week, Austin next week. Programming is not easy, and neither is parallel programming. Nevertheless, many people make it seem easy given the right tools and highly programmable machines. In Wellington at the New Zealand Multicore World Conference , I got to hear a number of thought provoking talks. Aside from great talks on HOW to do it, I love talks about what users accomplish with parallelism. Sebastian Sylwan ( WETA CTO) showed what they do with lots of parallelism. Tim Cornwell gave a talk entitled “Data Processing Algorithms: Legacy code will die” to provoke thinking around how today’s non-scalable algorithms are outdated and require rethinking. The organizers plan to post the talks, maybe the videos, I’ll post a links when that happens and comment then on the HOW papers which were interesting too. Next week, the ” TACC-Intel Highly Parallel Computing Symposium ” should be interesting. I do not want to steal thunder from the presenters, so I’ll wait to post comments on their talks afterwards. All the talks are investigation results using either the Intel research platform based on our research chip known as ” Single-Chip Cloud Computer (SCC) ” or on the more recent Knights Ferry prototype systems using the Intel Many Integrated Core (MIC) architecture . I know that the MIC papers will help highlight the enormous benefits of a highly programmable architecture, while exploring the challenges of parallel programming. The results speak for themselves: parallel programming is hard enough, the solutions should not abandon general programmability.  The good news… we don’t have to give up on being generally programmable. The bad news… high performance programming is not going to switch from hard work to being easy.

Does the Ultrabook Definition Need Tightening?

As the man behind Ultrabooknews.com I think about Ultrabooks multiple times every single day. I think about what’s happening in the public eye but I also focus carefully on what’s going, or could be going on, behind the scenes. I take comments from my readers seriously too but the hardest part is trying to balance what Intel, manufacturers, bloggers, journalists and fans say with what might be important for the silent majority, the mainstream that Intel and their partners will have to target in order to have a chance of making this Ultrabook thing , a complete change in the way laptops are made, succeed. Price is clearly a major consideration and I have no doubt that prices will reach mainstream levels. In fact, in the long-term, the Ultrabook design and production methodology could turn out to be cheaper than a traditional laptop but what does make me pause for thought is the definition of an Ultrabook and how important that is for the mainstream. Does Joe Average need to know exactly what an Ultrabook is or, like the expression ‘SUV’ is it something that can help customers find their way in the market? The mainstream user hasn’t really heard much about the ‘Ultrabook’ yet and given that there’s an average 3 year+ update period for laptops, many won’t hear about Ultrabooks until 2013 or 2014. At that point, every category of the laptop market will have moved-on in significant ways. Design, weight, battery life, style, operating systems, features – all part of the ‘Ultrabook effect’ and that, for everyone, is the most important result. Having ‘Ultrabook’ defined as a 13″ 1.3KG SSD-only Windows 8 laptop isn’t going to help anyone. It’s important that the Ultrabook methodology touches every segment of the laptop market and while that may not please onlookers who want everything to happen in their favorite segment, every customer needs to be catered for. The Ultrabook isn’t a specialist laptop product; The Ultrabook is a mainstream laptop event.

New face on our Intel® vPro™ Developer Community Page

Yes, that is a new face on your Intel® vPro™ Developer Community page. My name is Paul Steinberg. I have been working at Intel for more than 10 years now, seems like only 10 weeks though. For the last few years, I have been the Intel Academic Community Manager. In fact, I still am. At Intel, if you do good work, you are rewarded by . . . more work. In like manner, erstwhile VPro Community Manager, Kathy Farrel, has been promoted to VPro Program Manager. Congratulations Kathy! So what does the new face portend? For the moment not too much. I am hard at work now coming up to speed on our manageability technologies, on our VPro Developer Community members and of course, your needs. I am speaking now with the likes of Ylian Saint Hillaire and Gael Holmes Hofemeier . It is nice to have world class experts like these so close at hand. We will continue ensuring that the content, technical articles, videos and code sample are here. We will soon be starting a new video series, most likely hosted by both Gael and myself. The series will address real problems and solutions relevant to our community of developers. I would very much like to feature community members as well. If you have an idea for a guest or a topic, please let me know. You can reach me through this blog or the forums . Feel free to ask for my email if you want to contact me directly. And the future? Well, one thing that interests me is the confluence of manageability and security. How will that impact application development and what will that mean to you as developers? Do you have ideas? Let us know. I look forward to working with you all.

Serial Equivalence of Cilk Plus programs

The serial equivalence of a Cilk™ Plus parallel program There is a trend in the C++ community to grow capabilities thru more libraries and as much as possible, avoid adding language keywords. Consistent with these trends are Intel’s Threading Building Blocks and Microsoft’s Parallel Patterns Library. The question arises, then, why implement Intel’s Cilk™ Plus as language extensions rather than a library? One of the answers is that the language is implemented by compilers, and compilers can provide certain guarantees. One such guarantee is serial equivalence. Every Cilk Plus program that uses the 3 taking keywords for parallelism has a well-defined serial elision. The serial elision is defined by replacing each cilk_spawn and each cilk_sync with white spaces, and each cilk_for with the for keyword. Obviously, the serial elision of a Cilk Plus program is a valid C/C++ program. A program has a determinacy race if two logically parallel strands both access the same memory location and at least one of them modifies the memory location. If a Cilk Plus parallel program has no determinacy race, then it will produce the same results as its serial elision. What are the compiler’s contributions to the serial equivalence guarantees? Consider the following code illustration: int foo() {     int x1 = func1();     int d1 = 0;     int x2 = cilk_spawn child1(bar1(), bar2());  //spawn a funciton whose arguments are function calls     int x3 = cilk_spawn child2(&d1);                        // pass a stack address to a spawned function     int x4 = func3();                                                              // func3 can execute in parallel with child1 and child2    cilk_sync;                                                                          // wait for the child tasks to complete before their results can be used     return x1 + x2 + x3 + x4 + d1; } The function foo spawns the function child1() so that it can execute concurrently with the function func2(). The statement cilk_sync causes execution to wait until child1 and child2 return, so that their return values can be used. The compiler makes 3 contributions that determine the execution of the code here: 1. The functions bar1() and bar2(), which produce values that are arguments to child1(), are evaluated sequentially by the parent thread, i.e. the same thread on which the function foo executes. A different execution models would allow them to execute in parallel to each other, or on a thread that is different from the parent thread. However, only this execution model corresponds to the way in which the underlying, C/C++ languages work. 2. The compiler inserts a cilk_sync statement before the return statement in function foo(). The compiler inserts such a statement before the return of every function that includes a cilk_spawn. This enforces structured fork – join parallelism. It makes the program behavior easier to understand. On the practical side, the “implicit” cilk_sync inserted by the compiler ensures that the stack frame of foo() is in place throughout the execution of functions it spawns. In this illustration, since foo passed the address of d1 to child2(), it guarantees that when child2 writes into the location of d1, the memory location is as expected, in the stack of foo(). 3. The thread that executes foo proceeds to execute child1(). The continuation of foo(), starting from the statement that follows the cilk_spawn statement, is what it enqueued for later execution and being made available for stealing by other threads. This is called ‘parent stealing’. Library implementations of work stealing use ‘child stealing’. In this illustration, child stealing would mean that child1() would be enqueued for later evaluation and be made available for other workers to steal. However, only parent stealing is equivalent to the execution of the sequential program. Here is an example with a small code fragment that actually does something. Assume you have a ternary tree, in which nodes points to left, middle and right child nodes, and in addition have a color.  A linked list of all red nodes can be constructed with a recursive traversal of the tree, where each red node gets pushed onto a forming linked list. When parallelizing the recursion, care has to be taken not to create a data race when pushing nodes onto the global linked list. The recommended way to resolve the data race in Cilk Plus is to use a hyper object for the linked list. The hyper object provides a local view for each strand. A possible implementation of the parallelized recursion is here: cilk::reducer_list_append root; void find_reds_par(terntreenode *p) {       if (p-> color == red) {         root.push_back(p);       }       if (p-> left) cilk_spawn find_reds_par(p-> left);       if (p-> middle) cilk_spawn find_reds_par(p-> middle);       if (p-> right) find_reds_par(p-> right); }      The cilk Plus parallel traversal will produce the same linked list, with the same order of nodes, as the serial elision of the program.

Meshcentral.com – Win8 Metro Prototype Application

A few weeks back I started on a new quest to build a Windows 8 Metro application for Meshcentral.com . At least, learn about how to build such an app and get ready for when developers can submit free applications on the Microsoft Store. Well, I worked a few days using Javascript libraries I already use for Meshcentral’s web site and the Android and iPhone/iPad applications and developed my first Windows8 Metro Application. There is still plenty to work on, but I started running around Intel showing it off and figured I would make a small video showing it off. The video demonstrates the application on an EXO-PC tablet with the latest Windows 8 Consumer Preview and Visual Studio 2011 BETA. I started with a basic project that is provided with VS2011 and hacked it quite a bit. The result is very nice. Still bugs to work out but the speed is decent and it actually does work. This app is not yet available to the public, but hopefully the Microsoft Store will open soon. Youtube video at: http://www.youtube.com/watch?v=WJPVOAoBYzo Ylian Meshcentral.com

Jeff’s Notebook: The Developer’s Guide to Creating Intel® AMT Certificates for Intel® vPro™ clients

One of the great features of the latest Intel® vPro™ technology-based clients is that it supports the encryption of communications that an IT manager would have between the management console and the vPro client.  In order to enable this capability, a developer needs to work with a feature of vPro technology, called Intel® Active Management Technology (Intel® AMT).  Intel AMT is a capability embedded in Intel vPro technology based clients that enhance the ability of IT organizations to manage enterprise computing facilities.  Using  the Transport Layer Security (TLS), Intel AMT supports the encryption of communications between the management console and clients.  Enabling TLS communications requires the creation of Intel AMT security certificates.  While developers may not be aware of this process, it is a straightforward process.  Gael Hofemeier and Matt Gillespie have written a very thorough guide that gives developers the background and step-by-step procedures to create Intel AMT security certificates.    Read their guide to discover the step-by-step process.