Posts Tagged ‘Design’

A4 Flash Menu Builder

A4 Flash Menu Builder is an all-in-one, easy-to-use, templates-based Flash Menu Building software. It helps you to create professional looking Flash menus in minutes. No Flash programming, scripting, or design skills required. A4 Flash Menu Builder Main Features: Design Easy creation of… [ Web Flash Design ]

TBB adoption in CAD: Technical Insights

Working in software engineering, it is always important to be connected to your customers. Not only does it give you extra motivation from observing how your product helps them, but first of all, it allows you to better understand usage models, specific environment, potential issues and bring back the feedback to the team and improve the product. In this regard, I was especially glad to work with the engineering team of the OPEN CASCADE company who develops an open source 3D modeling kernel Open CASCADE Technology (OCCT) for CAD/CAM/CAE applications. A while ago OPEN CASCADE started using Intel® Parallel Studio , adopting Amplifier and Inspector. Last year the team started investigating Intel TBB and adopted it in a public release of OCCT 6.5 announced in March. This post will give some technical background of TBB usage in Open CASCADE. OCCT originates from mid-1990es and until now its huge legacy code base was single threaded. To break-through into multi-threading, it was important to focus on right directions and achieve impactful results with limited investments. Two core algorithms were addressed in a first place: 1. Memory management 2. 3D model tessellation Memory management OCCT has its own memory manager based on caching and reusing memory chunks. However its original design back in 1990-es was tailored to a single-threaded mode. In some recent version, it was made thread-safe with introduction of a coarse-grain lock protecting a chunk list. Certainly this design did not allow scaling in multi-threaded scenarios. The charts below compares scalability of a few allocators – Standard (OS), OCCT, and TBB, on different Windows versions (and different hardware). The workload involved a surface meshing (tessellation) algorithm from OCCT 6.3.1 executed on a complex 3D model. Even if the workload itself contained imbalances (e.g. planar and NURBS surfaces), and linear scalability was not expected, the results were convincing enough to conclude on potential benefits for other workloads. So, obviously the coarse-grain lock in the OCCT allocator virtually serialized the execution and killed scalability. Therefore adoption of a scalable TBB memory allocator was a reasonable choice. Moreover, since OCCT already enabled switching memory allocator in load-time, integration of TBB allocator was very simple – via subclassing an abstract adaptor class. Here is a code excerpt from OCCT 6.5: Standard_Address Standard_MMgrTBBalloc::Allocate(const Standard_Size aSize) { // the size is rounded up to 4 since some OCC classes // assume memory to be double word-aligned const Standard_Size aRoundSize = (aSize + 3) & ~0×3; Standard_Address aPtr = ( myClear ? scalable_calloc(aRoundSize, sizeof(char)) : scalable_malloc(aRoundSize) ); if ( ! aPtr ) Standard_OutOfMemory::Raise(“Standard_MMgrTBBalloc::Allocate(): malloc failed”); return aPtr; } 3D model tessellation Tessellation is an approximation with the help of surface triangulation and is used in visualization component of OCCT. The image below shows a sample 3D model and its underlying triangles: Visualization component is used in virtually every OCCT-based application, and thus, making this algorithm concurrent would naturally bring the greatest impact. Due to data model specificities, child sub-shapes are often dependent. For instance, an edge of a box is shared by its owning faces and hence, two faces cannot be independently tessellated. This may significantly limit scalability. Nonetheless, the first version will already take advantage of concurrent execution of data-independent iterations. Like in the case of the TBB allocator, integration was very compact and required just a few lines of code change: void BRepMesh_FastDiscret::Perform(const TopoDS_Shape& shape) { std::vector aFaces; . . . // mesh faces in parallel threads using TBB if (Standard::IsReentrant()) tbb::parallel_for_each (aFaces.begin(), aFaces.end(), *this); else for (std::vector::iterator it(aFaces.begin()); it != aFaces.end(); it++) Process (*it); } /* Processes the given face.*/ void BRepMesh_FastDiscret::operator ()(const TopoDS_Face& face) const { Process (face); } /* Processes the given face.*/ void BRepMesh_FastDiscret::Process(const TopoDS_Face& theFace) const { . . . } The following chart demonstrates scalability of the TBB-based tessellation algorithm measured on a couple of relatively large models: Limited scalability is mainly attributed to concurrent execution of only a sub-part of the entire algorithm (and hence an effect of the Amdahl’s law ). Conclusion Initial integration of TBB required very limited code changes in the OCCT sources but should benefit virtually all users of OCCT-based applications. Of course, we will look forward to extending TBB presence in OCCT!

Parallel Programmint Talk #103 – Dr. Martin Margala and Dr. Wim Vanderbauwhede – High-throughput DCT Algorithm, Using more than 1000 Processors

  Hi – it’s Tuesday, March 29 and this is show #103. We’ve been away for nearly a month as the film crew has been galivanting all over the place – from Barcelona to San Francisco. Bet they’re glad to be back in the Studio. I know I’m glad – we can return to the routine!……… We’ve got an interesting show planned for today – Drs Martin Margala and Wim Vanderbauwhede are here to talk about their project – a high-throughput DCT algorithm  using over 1000 processors. But first, the news: If you haven’t heard about it, The Intel Concurrency Checker is a free software assessment tool that Intel is offering to developers to help measure the level of concurrency that an application has.  When you use the tool and upload your code file to Intel, you’ll get an anonymous comparison of how the app’s measurement compares to other applications that were uploaded. It will also  provide suggested programming resources that a developer could use to help improve that app.  Want to see how other companies have benefitted – You can read case studies on four developer companies that have used the Intel Concurrency Checker.  To find them: http://software.intel.com/en-us/articles/case-studies-intel-concurrency-checker Many viewers have asked if there will be a Threading Challenge 2011 – The answer is Yes! The contest will start April 18 – details will be on the home page soon – so keep checking back for details – software.intel.com/parallel. We had out PP Community Meetup last week in Santa Clara – thanks to all the guests who braved the really wet weather – and there were a lot – they made it a terrific event.  We gave away a couple of Netbooks, had some interesting demos and an excellent presentation, by Intel Engineers Rich Hubbard and Noah Clemons,  on the workings of the 2 nd Generation Intel® Core™ Processor Family – AKA SandyBridge. We’ve captured the entire presentation on video and we will post it as soon as it’s available. We’ve got other videos from the meetup to post as well. Were you there – You might see yourself on a video or two. Let me tell you about today’s guests: Dr. Wim A. Vanderbauwhede received a PhD in Electrotechnical Engineering from the University of Gent, Belgium in 1996. He is a Lecturer (US equiv. Associate Professor) at the School of Computing Science of the University of Glasgow, which he joined in 2004. His research interests include programming concepts and architectures for many-core Systems-on-Chip, coarse-grained dynamically reconfigurable systems and FPGAs. His research has resulted in over 50 refereed conference and journal papers. Before returning to academic research, Dr Vanderbauwhede was an ASIC Design Engineer and Senior Technology R&D Engineer for Alcatel Microelectronics. Wimvanderbauwhede Dr Wim Vanderbauwhede School of Computing Science University of Glasgow 18 Lilybank Gardens, S122 Glasgow G12 8QQ, UK http://www.dcs.gla.ac.uk/~wim Prof. Martin Margala, Ph.D. has been an Associate Professor at the Electrical and Computer Engineering Department, University of Massachusetts Lowell and a Co-Director of the Advanced Electronics Technology Center (AETC) since 2007. Between 1997 and 2006 he was was an Assistant Professor at the University of Alberta, Cnada and the University of Rochester, NY respectively. He received his PhD degree in Electrical and Computer Engineering from the University of Alberta in the spring of 1998. He’s a senior member of IEEE with 160 journal and peer reviewed conference publications in the areas of Design for Testability of High Frequency Circuits and Systems, High-Performance Reliable Low-Power Architectures and Terahertz Circuits and Architectures. Associate Professor Electrical and Computer Engineering Department 301 Ball Hall University of Massachusetts Lowell One University Avenue Lowell, MA 01854 ph: (1) 978-934-2986 fax: (1) 978-934-3027 Additional Links on Martin and Wim’s project: Scientists squeeze more than 1,000 cores on to computer chip New chip to make computers ‘faster and greener’ Glasgow Scientists Build 1000-Core PC Processing Chip Academics develop super-fast 1,000 core FPGA chip ———————————————– Questions we asked: 0. What were you hoping to accomplish/discover with this project? 1. How were the 1000 cores assembled?  What technology was used?  2. How simple/complex are the cores?  3. How is this chip programmed?  4. What did you learn?  5. What’s next?  ———————————–  Did you know that there are other cool shows on ISN-TV – you should check them out – the ISN Academic Community Manager Paul Steinberg co-hosts Teach Parallel with Dr. Tom Wolfe from Contra Costa College – tune in next  week on Wednesday morning as Paul and Tom interview the Academic Community’s newest ISN black belt – professor Dick Brown. “Visualize This!” host Arti Gupta will speak with Intel AE Phil Taylor on the game samples being produced by his team. These are SNB samples that were released this year like Shadow Explorer and AVX Cloth.  Phil will also speak to what is upcoming this year.  This show will be available with Arti’s blog post on April 5 th .  FYI – PPT’s new show schedule is every other Tuesday with a show at 9am and another at 10am Join us next time –  Tuesday, April 12 at 9 and 10am Pacific – details for the shows will be on the community calendar. Be sure to drop us a line at – Clay – what’s that address? parallelprogrammingtalk@intel.com  And remember: “If you find yourself hanging by a thread, add some synchronization”

CurrPorts

CurrPorts displays the list of all currently opened TCP/IP and UDP ports on your local computer. For each port in the list, information about the process that opened the port is also displayed, including the process name, full path of the process, version information of the process (product name,… [ Network Design ]

EMCO Remote Registry Exporter

EMCO Remote Registry Exporter is a utility for network administrators, that enables you to export specified registry keys from a remote machine, and save them to a local folder. The program can be useful to backup specific keys, or to view the contained information while offline. It can detect… [ Network Design ]

Kinect hackers give us iOS-friendly dodgeball and Human Tetris

Remember that Microsoft Rally Ball demo from a few days ago that showed Windows Phone 7′s integration with Xbox? Well, the gang at Supertouch has stolen a bit of Ballmer’s thunder with a new Kinect hack that lets you hurl digital orbs at your Kinect-controlling friend using an iOS device instead of a WP7 handset. The graphics for the game and the iDevice controls aren’t nearly as pretty as Microsoft’s cross-platform gaming solution, but the end result is pretty much the same — flingin’ balls with a phone while your friend dodges them courtesy of Kinect. Meanwhile, Frog Design has added a Human Tetris game to the Kinect’s repertoire where players perfect their Vogue-ing skills by striking a pose to match an approaching cut-out on screen. Finally, all the shape-shifting fun with none of the goofy silver jumpsuits. Vids are after the break. [Thanks to everyone who sent these in] Continue reading Kinect hackers give us iOS-friendly dodgeball and Human Tetris Kinect hackers give us iOS-friendly dodgeball and Human Tetris originally appeared on Engadget on Sun, 20 Feb 2011 12:14:00 EDT. Please see our terms for use of feeds . Permalink

VisualRoute Lite Edition

The graphical report shows the network route from your computer to your destination, identifies the network devices along the route and shows where any data loss or slow response occurs. VisualRoute Lite Edition analyzes your Internet connection and identifies where problems occur, determining if… [ Network Design ]

Notion Ink Adam hits the FCC, torn apart in haste

Although Rohan told us that his Adam tablet had cleared FCC testing a few weeks ago, it’s not until today, just now actually, that we’ve seen the filing go public. For our troubles the FCC has done us the solid of a full-blown teardown. And honestly, it’s not pretty. Perhaps we shouldn’t be surprised to see so many hand-soldered connections and individual strands of wire encompassing the NVIDIA Tegra T20-H-A0 application processor and embedded Ericsson F3307 HSPA broadband module — it is, after all, the tiny startup’s first mass-market device. But we’ve borne witness to many a splayings including the tidy tablet teardowns of the iPad and Galaxy Tab . As such, the Adam comes across as a bedraggled mess of suspect build quality — great for modders, less great (potentially) for the average I-just-want-it-to-work consumer. Naturally, NI doesn’t have the design or manufacturing muscle of Apple or Samsung and with the tablet having only just now shipped it’ll be months before we have a good idea about the device’s integrity. So kick back for now with a few of the more egregious components (like the swiveling camera) after the break with the rest piled up in the gallery below. Gallery: Notion Ink Adam hits the FCC, torn apart in haste Continue reading Notion Ink Adam hits the FCC, torn apart in haste Notion Ink Adam hits the FCC, torn apart in haste originally appeared on Engadget on Fri, 28 Jan 2011 05:59:00 EDT. Please see our terms for use of feeds . Permalink

My Parallel Junkie Enabler

I love my wife. You may recall that for my 2008 birthday she got me Introduction to Algorithms, 3E . She knows how to feed my “addiction” for parallel programming knowledge and books. For Christmas this year she got me a copy of  Introduction to Parallel Computing, 2E , by Grama, Gupta, Karypis, and Kumar. I have the first edition of their book ( Introduction to Parallel Computing: Design and Analysis of Algorithms [1994]) and I used it when I was teaching at University of Southern Mississippi and when I was working for the Department of Defense contracts. When I first saw that a new version was published (2003), I meant to get it. It’s been on my Amazon Wishlist for quite a few years. But, as my work moved out of HPC, though, I found I was no longer needing to consult the text. As mentioned at the outset of the Preface of the second edition, the world of parallel computing has changed. This latest version includes information on Pthreads and OpenMP, so the book has again become relevant to what I’m doing now. Better late than never, right? However, now that it has been 7+ years since this edition was published, I fear a third edition will soon be out and I’ll want to update my library again. I’m not sure if my wife will be willing to re-feed my habit so soon or make me go cold turkey.

Preparing for Extreme Parallel Enviroments from a Student’s Perspective

Every student (including me!) upon graduation hopes their University has prepared them with all the skills to beat out the applicant sitting next to them for a job. Before joining as an intern with the Intel Academic Community, my conception of parallelism was to the say the least hazy. It was something I had at some point heard in lecture and buried far in the back of my brain in case I had to define it on a test sometime in the future. Through my time as an Intern my relationship with parallelism has become, for lack of a better word, intimate. With more and more manufacturers shifting towards many-core platforms, parallelism is making a strong presence in today’s computer industry and, whether I liked it or not, it was a change I, and all computer science students, will have to reckon with. So, as a student in the middle of this whirlwind of change, it would be nice to know what the revised list of skills is to beat out that applicant sitting next to me for a job. Luckily for me, this year’s Supercomputing Conference had a panel session on just this issue. It was called ‘Preparing for Extreme Parallel Environments’ and it featured some of the greatest minds in academia and industry engaged in thought-provoking discussion on how industry and academia can prepare for a parallel world. This year’s SC10 panel addressed three main questions everybody involved was itching to have answered. 1.) What does Industry expect from academia to prepare students for the workforce? 2.) What Changes must occur in curriculum to support High Performance Computing (HPC) and Programming models? 3.) What programming models are needed to support HPC and Parallel Programming? The first panel breakout session was lead by Michael McCool (Intel) and Matt Wolf (Georgia Tech). This session sought to define what knowledge and skills Industry expected from graduating students seeking employment. Participants of this session acknowledged that HPC is a diverse field and there is a lot of information a student could potentially be expected to know. With that being said, a list of topics the ideal HPC grad would know as well as the ideal skill set of a recent college grad pursuing the position of HPC developer was generated. Topics the ideal recent HPC grad would know: • Computer Architectures (HW vs. SW) • Domain Expertise(for example: physics – simulate vs. modeling vs. analyze) • Engineering (design vs. manufacturing) • Business (search vs. trading) The ideal skill set for HPC Developer (College Grad Entry): • Specific language skills (two languages even better!) • Ability to reason about parallelism • At least have written a shared-memory parallel program • Know how to predict performance • Experienced in writing parallel programs Speaking from a student’s perspective both the above lists are quite daunting. It would be near impossible to cover that many topics in four years. Coincidently (not really), the panel’s discussion concluded with a look at whether six year would allow for enough time to cover all the above topics. The second panel session was kicked off by Dan Ernst (University of Wisconsin Eau-Claire) and Wen-mei Hwu (University of Illinois). The panel discussed what changes must occur in the curriculums of computational science programs to support HPC and programming models. To start off they identified challenges academia would need to overcome in order for any of these curriculum changes to occur and then moved on to highlighting opportunities for change in the curriculum. Challenges: • Need to overcome current inertia and get ball rolling with changes • Material too difficult to engage beginning students • Currently available material(e.g. textbooks) are out of date • Poor faculty readiness with material • Application of HPC(real world examples) are not presented enough to students Opportunities for change: • Pull HPC down to minor degree level (to be understood by even non-CS majors) • Degree Focus areas • Cooperative Capstone Projects between CS major and non-CS major or CS major and CS minor. • Encourage students to apply HPC to solve math, physics, and other department’s problems. Example: Link Math and CS through numerical apps and require problems to be solved using HPC The panel discussion was concluded by proposing that CS degrees are isolated because of the lack of understanding students have in applying their knowledge. For example students may study how to build a library without knowing its use or how it will be applied. Too much focus is placed on the mathematics/details of the computation; whereas, more focus needs to be placed on assisting students in making the connection between the knowledge and actually applying the knowledge they have learned. The last panel was directed by Ben Gaster (AMD) and Tim Mattson (Intel). The discussion here was centered on what programming models are needed to support HPC and Parallel Programming. The main take away from this panel was to urge developers to shift their attention from obsessing about which programming models should be created, and rather work on and perfect current software. Why? Because what people want are a small number of good standards that work and work well. The discussion participants listed OpenMP, OpenCL, and MPI as programming models that fit this standard. Further discussion revolved around how to actually make the models we have work better. Another point was that students are lacking understanding of the design patterns that parallel programming experts consider second nature and know like the back of their hand. It was recommended that class time needs to be taken to introduce and explain these design patterns in detail, because with that, understanding programming models will be easier. I thought the SC10 panel on parallelism was a huge success in educating students, professors and academia. Personally, the panel provided me with insight on the future of the computer science curriculum and what employers might expect of me in the future. The panel produced mixed emotions from a student’s perspective, some combination of excitement and nervousness. Though, I am excited for the possibilities that result from shifting to many-core platforms, the magnitude of curriculum changes and shifting expectations from industry are rather overwhelming. Regardless of all the uncertainty surrounding parallelism, there is one certainty: a guarantee that the future of the computer industry will be action packed. So, at the end of the day, how can I not be excited to get to be a part of all the action?